Figure 104. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow); Figure 105. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow); Repetition Counter - STMicroelectronics STM32F405 Reference Manual

Advanced-control timers (TIM1&TIM8)

Figure 104. Counter timing diagram, update event with ARPE=1 (counter underflow)

Figure 105. Counter timing diagram, Update event with ARPE=1 (counter overflow)

17.3.3

Repetition counter

Section 17.3.1: Time-base unit
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N+1 counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
524/1731
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
describes how the update event (UEV) is generated with
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