Table 214. Nand Bank Selections; Nor Flash/Psram Controller - STMicroelectronics STM32F405 Reference Manual

RM0090
Section name
Address section
Command section
Data section
The application software uses the 3 sections to access the NAND Flash memory:
•
To send a command to NAND Flash memory: the software must write the command
value to any memory location in the command section.
• To specify the NAND Flash address that must be read or written: the software
must write the address value to any memory location in the address section. Since an
address can be 4 or 5 bytes long (depending on the actual memory size), several
consecutive writes to the address section are needed to specify the full address.
• To read or write data: the software reads or writes the data value from or to any
memory location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.
36.5

NOR Flash/PSRAM controller

The FSMC generates the appropriate signal timings to drive the following types of
memories:
•
Asynchronous SRAM and ROM
–
–
–
•
PSRAM (Cellular RAM)
–
–
–
•
NOR Flash
–
–
–
The FSMC outputs a unique chip select signal NE[4:1] per bank. All the other signals
(addresses, data and control) are shared.
For synchronous accesses, the FSMC issues the clock (CLK) to the selected external
device only during the read/write transactions. This clock is a submultiple of the HCLK clock.
The size of each bank is fixed and equal to 64 Mbytes.
Each bank is configured by means of dedicated registers (see
The programmable memory parameters include access timings (see
for wait management (for PSRAM and NOR Flash accessed in burst mode).

Table 214. NAND bank selections

1X
01
00
8-bit
16-bit
32-bit
Asynchronous mode
Burst mode for synchronous accesses
Multiplexed or nonmultiplexed
Asynchronous mode
Burst mode for synchronous accesses
Multiplexed or nonmultiplexed
DocID018909 Rev 11
Flexible static memory controller (FSMC)
HADDR[17:16]
0x020000-0x03FFFF
0x010000-0x01FFFF
0x000000-0x0FFFF
Address range
Section 36.5.6).
Table 215) and support
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