Dma2D Registers - STMicroelectronics STM32F405 Reference Manual

Chrom-Art Accelerator™ controller (DMA2D)
Interrupt event
CLUT access error
Transfer watermark
Transfer complete
Transfer error
11.5

DMA2D registers

11.5.1 DMA2D control register (DMA2D_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
CEIE CTCIE CAEIE
Reserved
rw rw
Bits 31:18 Reserved, must be kept at reset value
Bits 17:16 MODE: DMA2D mode
Bits 15:14 Reserved, must be kept at reset value
Bit 13 CEIE: Configuration Error Interrupt Enable
Bit 12 CTCIE: CLUT transfer complete interrupt enable
Bit 11 CAEIE: CLUT access error interrupt enable
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Table 59. DMA2D interrupt requests (continued)
27 26 25
Reserved
11 10 9
TWIE TCIE
rw rw rw
This bit is set and cleared by software. It cannot be modified while a transfer is ongoing.
00: Memory-to-memory (FG fetch only)
01: Memory-to-memory with PFC (FG fetch only with FG PFC active)
10: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
11: Register-to-memory (no FG nor BG, only output stage active)
This bit is set and cleared by software.
0: CE interrupt disable
1: CE interrupt enable
This bit is set and cleared by software.
0: CTC interrupt disable
1: CTC interrupt enable
This bit is set and cleared by software.
0: CAE interrupt disable
1: CAE interrupt enable
DocID018909 Rev 11
Event flag
CAEIF
TWF
TCIF
TEIF
24 23 22 21
8 7 6 5
TEIE
Reserved
rw
Enable control bit
CAEIE
TWIE
TCIE
TEIE
20 19 18 17
4 3 2 1
ABORT SUSP
rs rw
RM0090
16
MODE
0
START
rs