Figure 253. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0 And Rxonly=0) In The Case Of Continuous Transfers; Figure 254. Txe/Rxne/Bsy Behavior In Slave / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers - STMicroelectronics STM32F405 Reference Manual

RM0090
Figure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and
Example in Master mode with CPOL=1, CPHA=1
SCK
MISO/MOSI (out)
TXE flag
Tx buffer
(write SPI_DR)
BSY flag
MISO/MOSI (in)
RXNE flag
Rx buffer
(read SPI_DR)
software software waits
writes 0xF1 until TXE=1 and
into SPI_DR writes 0xF2 into
SPI_DR
Figure 254. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,
Example in Slave mode with CPOL=1, CPHA=1
SCK
MISO/MOSI (out)
TXE flag
Tx buffer
(write to SPI_DR)
BSY flag
MISO/MOSI (in)
RXNE flag
Rx buffer
(read from SPI_DR)
software software waits
writes 0xF1 until TXE=1 and
into SPI_DR writes 0xF2 into
SPI_DR
RXONLY=0) in the case of continuous transfers
DATA1 = 0xF1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
cleared by software
0xF1 0xF2
set by hardware
DATA1 = 0xA1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
software waits software waits
until RXNE=1 until TXE=1 and
and reads 0xA1 writes 0xF3 into
from SPI_DR SPI_DR
RXONLY=0) in the case of continuous transfers
DATA 1 = 0xF1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
cleared by software
0xF1 0xF2
set by cleared by software
DATA 1 = 0xA1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
software waits software waits
until RXNE=1 until TXE=1 and
and reads 0xA1 writes 0xF3 into
from SPI_DR
DocID018909 Rev 11
DATA2 = 0xF2
set by hardware
cleared by software
0xF3
DATA 2 = 0xA2
cleared by software
0xA1
software waits
until RXNE=1
and reads 0xA2
from SPI_ DR
DATA 2 = 0xF2
set by hardware
cleared by software
0xF3
DATA 2 = 0xA2
cleared by software
0xA1
software waits
until RXNE=1
and reads 0xA2
SPI_DR from SPI_ DR
Serial peripheral interface (SPI)
DATA3 = 0xF3
set by hardware
reset by hardware
DATA 3 = 0xA3
0xA2
software waits
until RXNE=1
and reads 0xA3
from SPI_DR
DATA 3 = 0xF3
set by hardware
reset by hardware
DATA 3 = 0xA3
0xA2
software waits
until RXNE=1
and reads 0xA3
from SPI_DR
0xA3
ai17343
0xA3
ai17344
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