Analog-to-digital converter (ADC)
13.13.10 ADC regular sequence register 2 (ADC_SQR2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
Reserved
rw
15
14
13
SQ10_0
SQ9[4:0]
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence
Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence
13.13.11 ADC regular sequence register 3 (ADC_SQR3)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
28
Reserved
rw
rw
15
14
13
12
SQ4_0
SQ3[4:0]
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence
426/1731
28
27
26
25
SQ12[4:0]
rw
rw
rw
rw
12
11
10
9
rw
rw
rw
rw
These bits are written by software with the channel number
the sequence to be converted.
27
26
25
SQ6[4:0]
rw
rw
rw
11
10
9
rw
rw
rw
These bits are written by software with the channel number (0..18) assigned as the 6th in the
sequence to be converted.
DocID018909 Rev 11
24
23
22
21
SQ11[4:0]
rw
rw
rw
rw
8
7
6
5
SQ8[4:0]
rw
rw
rw
rw
24
23
22
21
SQ5[4:0]
rw
rw
rw
rw
8
7
6
5
SQ2[4:0]
rw
rw
rw
rw
20
19
18
17
SQ10[4:1]
rw
rw
rw
rw
4
3
2
1
SQ7[4:0]
rw
rw
rw
rw
(0..18)
assigned as the 12th in
20
19
18
17
SQ4[4:1]
rw
rw
rw
rw
4
3
2
1
SQ1[4:0]
rw
rw
rw
rw
RM0090
16
rw
0
rw
16
rw
0
rw
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