Spi Data Register (Spi_Dr); Spi Crc Polynomial Register (Spi_Crcpr) (Not Used In I; Mode - ST STM32F410 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
25.7.4

SPI data register (SPI_DR)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
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Bits 15:0 DR[15:0]: Data register
Note: These notes apply to SPI mode:
25.7.5

SPI CRC polynomial register (SPI_CRCPR) (not used in I

mode)

Address offset: 0x10
Reset value: 0x0007
15 14 13
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Bits 15:0 CRCPOLY[15:0]: CRC polynomial register
Note: These bits are not used for the I
726/771
12 11 10 9
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Data received or to be transmitted.
The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for
reading (Receive buffer). A write to the data register will write into the Tx buffer and a read
from the data register will return the value held in the Rx buffer.
Depending on the data frame format selection bit (DFF in SPI_CR1 register), the data
sent or received is either 8-bit or 16-bit. This selection has to be made before enabling
the SPI to ensure correct operation.
For an 8-bit data frame, the buffers are 8-bit and only the LSB of the register
(SPI_DR[7:0]) is used for transmission/reception. When in reception mode, the MSB of
the register (SPI_DR[15:8]) is forced to 0.
For a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is
used for transmission/reception.
12 11 10 9
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This register contains the polynomial for the CRC calculation.
The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be
configured as required.
8 7 6
DR[15:0]
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8 7 6
CRCPOLY[15:0]
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2
S mode.
RM0401 Rev 3
5 4 3 2
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2
S
5 4 3 2
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RM0401
1 0
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1 0
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