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RM0402
Bits 23:16 DATA6[7:0]
Data byte 2 of the message.
Bits 15:8 DATA5[7:0]
Data byte 1 of the message.
Bits 7:0 DATA4[7:0]
Data byte 0 of the message.
28.9.4
CAN filter registers
CAN filter master register (CAN_FMR)
Address offset: 0x200
Reset value: 0x2A1C 0E01
All bits of this register are set and cleared by software.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
rw
Bits 31:14
Reserved, must be kept at reset value.
Bits 13:8
CANSB[5:0]
These bits are set and cleared by software. When both CAN are used, they define the start
bank of each CAN interface:
Bits 7:1
Reserved, must be kept at reset value.
Bit 0
FINIT
CAN filter mode register (CAN_FM1R)
Address offset: 0x204
Reset value: 0x0000 0000
This register can be written only when the filter initialization mode is set (FINIT=1) in the
CAN_FMR register.
:
Data Byte 6
:
Data Byte 5
:
Data Byte 4
28
27
26
25
Res.
Res.
Res.
12
11
10
9
CANSB[5:0]
rw
rw
rw
rw
:
CAN start bank
000001 = 1 filter assigned to CAN1 and 27 assigned to CAN2
011011 = 27 filters assigned to CAN1 and 1 filter assigned to CAN2
–
to assign all filters to one CAN set CANSB value to zero and deactivate the non
used CAN
–
to use CAN1 only: stop the clock on CAN2 and/or set the CAN_MCR.INRQ on
CAN2
–
to use CAN2 only: set the CAN_MCR.INRQ on CAN1 or deactivate the interupt
register CAN_IER on CAN1
:
Filter initialization mode
Initialization mode for filter banks
0: Active filters mode.
1: Initialization mode for the filters.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
rw
RM0402 Rev 6
Controller area network (bxCAN)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
Res.
FINIT
rw
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