STMicroelectronics STM32WL5 Series Reference Manual page 1324

Debug support (DBG)
Bits 11:8 MASKLANE[3:0]: masked byte lanes
Indicates the bytes to be masked in pushed-compare and pushed-verify operations
(DP_CTRLSTATR.TRNMODE = 1 or 2). In the pushed operations, the word supplied in an
AP write transaction is compared with the current value at the target AP address.
1XXX = includes byte lane 3 in comparisons.
X1XX = includes byte lane 2 in comparisons.
XX1X = includes byte lane 1 in comparisons.
XXX1 = includes byte lane 0 in comparisons.
Bit 7 WDATAERR: write data error (read only) in SW-DP
There is a parity or framing error on the data phase of a write, or a write that has been
accepted by the DP is then discarded without being submitted to the AP.
This bit is reset by writing 1 to the DP_ABORTR.WDERRCLR bit.
0: No error
1: An error occurred.
Reserved in JTAG-DP.
Bit 6 READOK: AP read response (read only) in SW-DP
Indicates the response to the last AP read access.
0: Read not OK
1: Read OK
Reserved in JTAG-DP.
Bit 5 STICKYERR: transaction error (read only in SW-DP, R/W in JTAG-DP)
Indicates that an error occurred in an AP transaction.
0: No error
1: An error occurred.
In SW-DP, STICKYERR bit is read only, reset by writing 1 to the DP_ABORTR.STKERRCLR
bit.
In JTAG-DP, STICKYERR bit is read, cleared by writing a 1 to it.
Bit 4 STICKYCMP: match comparison (read only in SW-DP, R/W in JTAG-DP)
Indicates that a match occurred in a pushed operation.
0: match if TRNMODE = 0x1; no match if TRNMODE = 0x2
1: no match if TRNMODE = 0x1; match if TRNMODE = 0x2
In SW-DP, STICKYCMP bit is read only, reset by writing 1 to the DP_ABORTR.STKCMPCLR
bit.
In JTAG-DP, STICKYCMP bit is read, cleared by writing a 1 to it.
1324/1450 RM0453 Rev 5
RM0453