STMicroelectronics STM32WL5 Series Reference Manual page 1338

Debug support (DBG)
Offset Register name
0x08 Reserved
AP_DRWR
0x0C
Reset value
AP_BD0R
0x10
Reset value
AP_BD1R
0x14
Reset value
AP_BD2R
0x18
Reset value
AP_BD3R
0x1C
Reset value
0x20 to
Reserved
0xF4
AP_BASER
0xF8
Reset value (AP0)
Reset value (AP1)
AP_IDR
0xFC
Reset value (AP0)
Reset value (AP1)
38.6 Data watchpoint and trace unit (DWT)
The DWT provides four comparators that can be used as one of the following function:
•
watchpoint
•
PC sampling trigger
• data address sampling trigger
•
data comparator (comparator 1 only)
• clock cycle counter comparator (comparator 0 only)
It also contains counters for:
•
clock cycles
•
folded instructions
•
load store unit (LSU) operations
•
sleep cycles
•
number of cycles per instruction
•
interrupt overhead
1338/1450
Table 270. AP register map and reset values (continued)
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0
0 0 1 0 0 1 0 0 0
0 1 1 0 0 1 0 0 0
Reserved
TD[31:0]
0 0 0 0 0 0 0 0
TBD[31:0]
0 0 0 0 0 0 0 0
TBD[31:0]
0 0 0 0 0 0 0 0
TBD[31:0]
0 0 0 0 0 0 0 0
TBD[31:0]
0 0 0 0 0 0 0 0
Reserved
BASEADDR[19:0]
0 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0
JEDECCODE[6:0]
1 1 1 0 1 1 1
1 1 1 0 1 1 1
RM0453 Rev 5
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
0 0
RM0453
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 0 1 1
IDENTITY[7:0]
0 1 0 0 0 1
0 0 0 0 0 1