STMicroelectronics STM32WL5 Series Reference Manual page 1336

Debug support (DBG)
38.5.4 AP banked data registers x (AP_BDxR)
Address offset: 0x10 + 0x04 * x, (x=0 to 3)
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 TBD[31:0]: banked data of current transfer to address AP_TAR.TA
TA + AP_BDnR address [3:2] + 0b00
Auto address incrementing is not performed on AP_BD[3:0]R.
Banked transfers are only supported for word transfers.
38.5.5 AP base address register (AP_BASER)
Address offset: 0xF8
Reset value: 0xE00F F003 (AP0)
Reset value: 0xF000 0003 (AP1)
31 30 29
r r r
15 14 13
BASEADDR[3:0]
r r r
Bits 31:12 BASEADDR[19:0]: base address (bits 31 to 12) of ROM table for the AP
The 12 LSBs are zero since the ROM table must be aligned on a 4-Kbyte boundary.
AP0 CPU1 (Cortex-M4) AHB-AP: 0xE00FF
AP1 CPU2 (Cortex-M0+) AHB-AP: 0xF0000
Bits 11:2 Reserved, must be kept at reset value.
Bit 1 FORMAT: base address register format
1: Arm debug interface v5
Bit 0 ENTRYPRESENT: Indicates that debug components are present on the access port bus.
1: Debug components are present
1336/1450
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
28 27 26 25
r r r r
12 11 10 9
Res. Res. Res.
r
24 23 22
TBD[31:16]
rw rw rw
8 7 6
TBD[15:0]
rw rw rw
24 23 22
BASEADDR[19:4]
r r r
8 7 6
Res. Res. Res.
RM0453 Rev 5
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
r r r r
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
rw rw
1 0
rw rw
17 16
r r
1 0
ENTRY
FORM
PRESE
AT
NT
r r