STMicroelectronics STM32WL5 Series Reference Manual page 1332

Debug support (DBG)
The debugger can access the AP registers as follows:
1. Program in the DP_SELECTR register, the APSEL(3:0] field to choose one of the APs
and the APBANKSEL[3:0] field to select the register bank to be accessed (see
Section
2. Program the A(3:2) field in the APACC register, if using JTAG, with the register address
within the bank. Program the RnW bit to select a read or write. In the case of a write,
program the DATA field with the write data. If using SWD, the A(3:2) and RnW fields
are part of the packet request word sent to the SW-DP with the APnDP bit set (see
Table 264: Packet
The debugger can access the memory mapped debug component registers through the
MEM-AP registers (using the above AP register access procedure) as follows:
1. Program the transaction target address in the AP_TAR register.
2. Program the AP_CSWR register, if necessary, with the transfer parameters (AddrInc for
example).
3. Write to or read from the AP_DRWR register to initiate a bus transaction at the address
held in the AP_TAR register. Alternatively, a read or write to the AP_BDxR register
triggers an access to address AP_TAR[31:4] + x (allowing up to four consecutive
addresses to be accessed without changing the address in the AP_TAR register).
Figure 387
components (in this example a processor and a ROM table).
For more detailed information on the MEM-AP, refer to the Arm
Architecture Specification [1].
1332/1450
38.4.8).
request). The write data is sent in the data phase.
shows how the MEM-AP is used to connect the debug port to the debug
RM0453 Rev 5
RM0453
®
Debug Interface