Processor Connections; Power Mapping - Texas Instruments TPS65941213-Q1 User Manual

Processor Connections

3 Processor Connections
This section details how the dual TPS6594-Q1 power resources and GPIO signals are connected to the
processor and other peripheral components.

3.1 Power Mapping

Figure 3-1 shows the power mapping between the dual TPS6594-Q1 PMIC power resources and processor
voltage domains required to support independent MCU and Main power rails. In this configuration, both PMICs
use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that
connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the
PMICs.
For SD card dual-voltage I/O support (3.3 V and 1.8 V), LDO1 of the TPS65941111-Q1 device can be used.
A processor GPIO control signal with a logic high default value is used to set SD VIO to 3.3 V initially. During
processor power up, the boot loader SW can set GPIO signal low to select 1.8 V level as needed for high-speed
card operation per SD specification. This allows control of the LDO1 voltage without the need for the MCU
processor to establish I2C communication with the PMICs during boot from SD card operations.
This PDN uses four discrete power components with three being required and one is optional depending upon
end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply OV
protected 3.3 V to processor I/O domains. Two load switches are required in order to enable isolation between
MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The unused
feedback pin, FB_B3, of the TPS65941213 has been configured per NVM settings,
monitoring for VDD_MCUIO_3V3_LS power rail. This enables all of the MCU processor power supply inputs to
have voltage monitoring coverage as needed for functional safety ASIL-B and higher systems. The third discrete
device is a TPS62813-Q1 Buck Converter which supplies the LPDDR4 SDRAM component with required 1.1V
supply. The last discrete power component is an optional TLV73318-Q1 LDO that can be used if an end product
uses a high security processor type and desires the capability to program Efuse values on-board. If this feature
is not desired, then this LDO can be omitted and processor pins terminated per data manual recommendations.
The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. The VMON_ABIST_EN=1 for both
the primary and secondary PMICs. If 3.3 V is not connected to FB_B3 when the monitor is enabled
then the self-test fails, the BIST_FAIL_INT interrupt is set, and the device goes to the hardware SAFE
RECOVERY state, see
4 Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
Jacinto™ 7 J721E, PDN-0C
Note
Figure 6-1, and main processor voltages are disabled.
Copyright © 2022 Texas Instruments Incorporated
Table 5-3, to provide voltage
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
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