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2 Power Considerations
2.1 Power Pin Description and Internal Voltage Regulator
The PCIXX20 controller contains different types of power terminals; system designers must pay
close attention to the connections and power-up sequences of these terminals:
Terminal
AVD2, AVD3, AVD4
Analog circuit power terminals
V
Power supply terminal for I/O and internal voltage regulator. These terminals must all be tied to
CC
V
, V
Clamp voltage for PC Card interfaces. Matches socket signaling environment, 5 V or 3.3 V.
CCA
CCB
V
Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
CCP
VR_PORT
1.8-V output from internal voltage regulator when VR_EN is high, 1.8-V input when VR_EN is
low.
VDPLL
PLL circuit power terminal
The PCIXX20 controller uses an internal voltage regulator to power the core logic at 1.8 V. The
voltage regulator is enabled using the VR_EN terminal. If VR_EN is high, then the voltage
regulator is disabled and VR_PORT serves as a 1.8-V external input to power the core. If
VR_EN is low, then the internal voltage regulator is enabled, VR_PORT serves as a 1.8-V
output.
2.2 Device Power Sequence
Depending on the host platform, different device power sequences are required. For 5-V
tolerant systems, V
VR_PORT (1.8 V – only if internal voltage regulator is disabled). For 3-V tolerant systems, V
V
, VDPLL, and AVDx (3.3 V) must be supplied before supplying VR_PORT (1.8 V – only if
CCP
internal voltage regulator is disabled).
2.3 Bypass Capacitors
Standard design rules for the power supply bypass must be followed. The following sections are
bypass capacitors recommended by Texas Instruments.
2.3.1 V
, V
, V
CC
CCP
CCA
A 0.1-µF bypass capacitor is recommended for each of these power terminals.
Table 2.
Power Terminal Description
system-supplied 3.3-V power source.
(5 V) must be supplied first, then V
CCP
, and V
CCB
Description
CC
PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
, VDPLL, and AVDx (3.3 V), finally
SCPU019
,
CC
9
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