On-Chip Supporting Module Access Timing - Hitachi H8/3008 Hardware Manual

φ
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
φ
Address bus
AS RD HWR LWR
,
D to D
15
Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1)
2.9.3

On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting
module access timing. Figure 2.18 indicates the pin states.
52
Figure 2.15 On-Chip Memory Access Cycle
, ,
0
Bus cycle
T state
1
Address
Read data
Write data
T
1
Address
High
High impedance
T state
2
T
2