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6.4.5
Basic Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit,
three-state-access area. The upper data bus (D
LWR pin is always high. Wait states can be inserted.
Address bus
Read access
Write access
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
122
φ
CS
n
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
High
D
to D
15
8
D
to D
7
0
to D
) is used in accesses to these areas. The
15
8
Bus cycle
T
T
1
2
External address in area n
Valid
Undetermined data
T
3
Valid
Invalid
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