On-Chip Support Module Access Timing; On-Chip Hcan Module Access Timing; Figure 7.2 On-Chip Support Module Access Cycle; Figure 7.3 On-Chip Hcan Module Access Cycle (With Wait States) - Hitachi H8S/2628 Hardware Manual

7.1.2

On-Chip Support Module Access Timing

The on-chip support modules, except for the HCAN, SSU, and realtime input port data register,
are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular
internal I/O register being accessed. For details, refer to section 22, List of Registers. Figure 7.2
shows access timing for the on-chip peripheral modules.
φ
Internal address bus
Read
Write
7.1.3

On-Chip HCAN Module Access Timing

On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait
states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access
timing is shown in figures 7.3.
φ
Internal address bus
HCAN read signal
Read
Internal data bus
HCAN write signal
Write
Internal data bus

Figure 7.3 On-Chip HCAN Module Access Cycle (with Wait States)

Rev. 1.0, 09/02, page 94 of 568
Internal read signal
Internal data bus
Internal write signal
Internal data bus

Figure 7.2 On-Chip Support Module Access Cycle

T1
Bus cycle
T1
Address
Read data
Write data
Bus cycle
T2
T3
Tw
Address
Write data
T2
Tw T4
Read data