Operational Timing; Bus Timing - Hitachi H8/3035 Series Hardware Manual

17.3 Operational Timing

This section shows timing diagrams.

17.3.1 Bus Timing

Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 17-4 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 17-5 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 17-6 shows the timing of the external three-state access cycle with one wait state
inserted.
t
ø
t
A to A
23 0
AS
RD
(read)
D to D
7 0
(read)
WR (write)
t
D to D
7 0
(write)
Figure 17-4 Basic Bus Cycle: Two-State Access
T
1
t
cyc
t
CH CL
t
CF CR
t
AD
t t
ASD ACC3
t
AS1
t t
ASD ACC3
t
AS1
t t
ACC1 RDS
t
ASD
t
AS1
t
WSW1
t
WDS1
WDD
T
2
t
PCH
t t
SD AH
t
PCH
t t
SD AH
t
RDH
t
PCH
t t
SD AH
t
WDH
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