Figure 22.23 Basic Bus Cycle: Two-State Access - Hitachi H8/3062 Hardware Manual

φ
t
AD
A to A ,
23 0
CS
n
AS
RD
(read)
D to D
15 0
(read)
HWR, LWR
(write)
D to D
15 0
(write)
*
Note: Specification from the earliest negation timing of A
T
1
t
cyc
t t
CH CL
t
Cf
t
ASD
t
AS1
t
ASD
t
AS1
t
ACC1
t
ASD
t
AS1
t
WDD

Figure 22.23 Basic Bus Cycle: Two-State Access

T
2
t
Cr
t
cyc
t t
ACC3 SD
t
ACC3
t
RDS
t
SD
t
WSW1
t
WDS1
, CS , and RD.
to A
23 0 n
t
PCH1
t
AH
t
t
RSD
PCH2
*
t
RDH
t
PCH1
t
AH
t
WDH
757