Usage Notes; Contention Between Tcnt Write And Clear - Hitachi H8S/2338 Series Hardware Manual

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TCORA
TCORB
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9.6

Usage Notes

Note that the following kinds of contention can occur in the 8-bit timer module.
9.6.1

Contention between TCNT Write and Clear

If a timer counter clock pulse is generated during the T
takes priority, so that the counter is cleared and the write is not performed.
Figure 9-10 shows this operation.
ø
Address
Internal write signal
Counter clear signal
TCNT
Figure 9-10 Contention between TCNT Write and Clear
TCNT
Figure 9-9 Example of Pulse Output
TCNT write cycle by CPU
T
1
TCNT address
N
Counter clear
state of a TCNT write cycle, the clear
2
T
2
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