Conflict Between Tcnt Write And Clear Operations; Figure 10.45 Conflict Between Tcnt Write And Clear Operations - Hitachi H8S/2628 Hardware Manual

Where f : Counter frequency
φ : Operating frequency
N : TGR set value
10.9.4

Conflict between TCNT Write and Clear Operations

If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed.
Figure 10.45 shows the timing in this case.
φ
Address
Write signal
Counter clear
signal
TCNT

Figure 10.45 Conflict between TCNT Write and Clear Operations

Rev. 1.0, 09/02, page 232 of 568
TCNT write cycle
T1 T2
TCNT address
N H'0000