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9.7
Usage Notes
Note that the following kinds of contention can occur in 8-bit timer operation.
9.7.1
Contention between 8TCNT Write and Clear
If a timer counter clear signal occurs in the T
counter takes priority and the write is not performed. Figure 9.18 shows the timing in this case.
Address bus
Internal write signal
Counter clear signal
8TCNT
Figure 9.18 Contention between 8TCNT Write and Clear
T
1
φ
state of a 8TCNT write cycle, clearing of the
3
8TCNT write cycle
T
2
8TCNT address
N
T
3
H'00
309
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