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Clock
oscillator
ø
NMI
NMIEG
SSBY
NMI exception
handling
NMIEG = 1
SSBY = 1
Figure 16-1 NMI Timing for Software Standby Mode (Example)
16.4.5 Usage Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output current is not reduced.
16.5 Hardware Standby Mode
16.5.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the
goes low. Hardware standby mode reduces power consumption drastically by halting all
functions of the CPU and on-chip supporting modules. All modules are reset except the on-chip
RAM. As long as the specified voltage is supplied, on-chip RAM data is retained. I/O ports are
placed in the high-impedance state.
Clear the RAME bit to 0 in SYSCR before
The inputs at the mode pins (MD
mode.
388
Software standby
mode (power-
down state)
SLEEP
instruction
67%<
goes low to retain on-chip RAM data.
and MD
) should not be changed during hardware standby
1
0
Oscillator
NMI exception
settling time
handling
(t
)
osc2
67%<
pin
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