Bus Release; Overview - Hitachi H8S/2678 Series Reference Manual

Internal address bus
Internal read signal
A23 to A0
CSn
External
space
write
HWR, LWR
D15 to D0
Figure 4.53 Example of Timing when Write Data Buffer Function is Used
4.9

Bus Release

4.9.1

Overview

The H8S/2678 Series chip can release the external bus in response to a bus request from an
external device. In the external bus released state, internal bus masters (except the EXDMAC)
continue to operate as long as there is no external access.
If any of the following requests are issued in the external bus released state, the BREQO signal
can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode
174
On-chip
memory read
External write cycle
T T
1 2
Internal memory
External address
Internal I/O
register read
T T
W W
Internal I/O register address
T
3