Irq Status Register (Isr) - Hitachi H8S/2628 Hardware Manual

5.3.4

IRQ Status Register (ISR)

ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt
requests.
Bit Bit Name

7,
6
5 IRQ5F
4 IRQ4F
3 IRQ3F
2 IRQ2F
1 IRQ1F
0 IRQ0F
Rev. 1.0, 09/02, page 70 of 568
Initial Value R/W
All 0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
Only 0 should be written to these bits.
[Setting conditions]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
•
Cleared by reading IRQnF flag when IRQnF
= 1, then writing 0 to IRQnF flag
•
When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high
•
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
•
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0