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Bits 15 to 0—IRQ15 Sense Control A and B (IRQ15SCA, IRQ15SCB) to IRQ0 Sense
Control A and B (IRQ0SCA, IRQ0SCB)
IRQnSCB
IRQnSCA
0
0
1
1
0
1
3.3.5
IRQ Status Register (ISR)
Bit
15
IRQ15F
Initial value
0
Read/Write
R/(W)*
Bit
7
IRQ7F
Initial value
0
Read/Write
R/(W)*
Note: * Only 0 can be written, to clear the flag.
ISR is a 16-bit readable/writable register that indicates the status of IRQ15 to IRQ0 interrupt
requests.
ISR is initialized to H'0000 by a reset and in hardware standby mode.
As IRQnF may be set to 1 depending on the pin states after a reset, it is necessary to read ISR, and
then write 0s to it, following a reset.
62
Description
Interrupt request generated at IRQn input low level
Interrupt request generated at falling edge of IRQn input
Interrupt request generated at rising edge of IRQn input
Interrupt request generated at both falling and rising edges of IRQn
input
14
13
IRQ14F
IRQ13F
0
0
R/(W)*
R/(W)*
6
5
IRQ6F
IRQ5F
0
0
R/(W)*
R/(W)*
12
11
IRQ12F
IRQ11F
0
0
R/(W)*
R/(W)*
4
3
IRQ4F
IRQ3F
0
0
R/(W)*
R/(W)*
(Initial value)
(n = 15 to 0)
10
9
IRQ10F
IRQ9F
0
0
R/(W)*
R/(W)*
2
1
IRQ2F
IRQ1F
0
0
R/(W)*
R/(W)*
8
IRQ8F
0
R/(W)*
0
IRQ0F
0
R/(W)*
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