Figure 6-5 Simultaneous Instruction And Data Requests; Simultaneous Instruction And Data Request - ARM ARM966E-S Technical Reference Manual

Bus Interface Unit
CLK
HTRANS
HADDR
HWRITE
HRDATA
HWDATA
HREADY
6-10
Even though the transfers are to sequential addresses, each access is treated as a separate
nonsequential transfer. Figure 6-4 on page 6-9 assumes that all instruction fetches from
the ARM9E-S core are being serviced by the I-SRAM.
Note
An identical series of NONSEQ or IDLE transfers is seen if executing a sequence of
back-to-back STR instructions.

Simultaneous instruction and data request

When the ARM9E-S makes a simultaneous instruction and data request, both resident
in AHB memory, the BIU must arbitrate between the two accesses. The data access is
always completed first, stalling the ARM9E-S until the instruction fetch completes.
Figure 6-5 shows an example of an
and data request.
IDLE NONSEQ
IA-3
ID-1
During the cycle that [IA-3] is first driven onto HADDR, the BIU detects a
simultaneous data request. [IA-3] fetch is suspended until the data access has
completed.
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instruction causing a simultaneous instruction
STR
IDLE NONSEQ NONSEQ
DA-1
ID-2

Figure 6-5 Simultaneous instruction and data requests

IDLE NOSEQ
IA-3 IA-4
ID-3
DD-1
ARM DDI 0186A
IDLE