Bar1 Register; Bar1 Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

13.4.6.3 BAR1 Register

The base address register 1 (BAR1) is described in the figure and table below.
31
7 6
Base Address
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-7 Base Address 0-1FF FFFFh
6-4 Reserved
3 Prefetchable
2-1 Type
0 Memory Space
13.4.6.3.1 BAR1 Register
The base address register 1 (BAR1) is described in the figure and table below.
31
LEGEND: R/W = Read/Write; -n = value after reset
Bit Field
31-0 Base Address
1348
Peripheral Component Interconnect Express (PCIe)
Preliminary
Figure 13-79. BAR1 Register
Base Address
4
Reserved
R-0
Table 13-84. BAR1 Register Field Descriptions
Value Description
Base Address
0 Reserved
0 For memory BARs, it indicates whether the region is prefetchable. For IO Bars, it is used as
second LSB of the base address. Writable from internal bus interface.
0-3h Decode type. Writable from internal bus interface.
0 32 bit decode
1h Reserved
2h 64 bit decode
3h Reserved
0 Set to indicate Memory Space. Writable from internal bus interface.
Figure 13-80. BAR1 Register
Base Address
Table 13-85. BAR1 Register Field Descriptions
Value Description
0-FFFF FFFFh Upper 32 bits of BAR0 address
© 2011, Texas Instruments Incorporated
R/W-0
3 2
Prefetchable Type
R-1
R/W-0
www.ti.com
1 0
Memory Space
R-0 R-0
SPRUGX9 – 15 April 2011
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