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Architecture
The bit mask and pad stage includes a full 32-bit mask register, allowing selected individual bits to
either pass through the stage unchanged, or be masked off. The bit mask and pad then pad the value
of the masked off bits by inserting either a 0, a 1, or one of the original 32 bits as the pad value. The
last option allows for sign-extension when the sign bit is selected to pad the remaining bits.
The rotate right stage performs bitwise rotation by a multiple of 4 bits (between 0 and 28 bits),
programmable by the (R/X)FMT register. Note that this is a rotation process, not a shifting process, so
bit 0 gets shifted back into bit 31 during the rotation.
The bit reversal stage either passes all 32 bits directly through, or swaps them. This allows for either
MSB or LSB first data formats. If bit reversal is not enabled, then the McASP will naturally transmit and
receive in an LSB first order.
Finally, note that the (R/X)DATDLY bits in (R/X)FMT also determine the data format. For example, the
difference between I2S format and left-justified is determined by the delay between the frame sync
edge and the first data bit of a given time slot. For I2S format, (R/X)DATDLY should be set to a 1-bit
delay, whereas for left-justified format, it should be set to a 0-bit delay.
The combination of all the options in (R/X)FMT means that the McASP supports a wide variety of data
formats, both on the serial data lines, and in the internal processor representation.
Section 10.2.8.3
provides more detail and specific examples. The examples use internal representation
in integer and Q31 notation, but other fractional notations are also possible.
10.2.7.3 State Machine
The receive and transmit sections have independent state machines. Each state machine controls the
interactions between the various units in the respective section. In addition, the state machine keeps
track of error conditions and serial port status.
No serial transfers can occur until the respective state machine is released from reset. See initialization
sequence for details
The receive state machine is controlled by the RFMT register, and it reports the McASP status and
error conditions in the RSTAT register. Similarly, the transmit state machine is controlled by the XFMT
register, and it reports the McASP status and error conditions in the XSTAT register.
10.2.7.4 TDM Sequencer
There are separate TDM sequencers for the transmit section and the receive section. Each TDM
sequencer keeps track of the slot count. In addition, the TDM sequencer checks the bits of (R/X)TDM
and determines if the McASP should receive/transmit in that time slot.
If the McASP should participate (transmit/receive bit is active) in the time slot, the McASP functions
normally. If the McASP should not participate (transmit/receive bit is inactive) in the time slot, no
transfers between the XRBUF and XRSR registers in the serializer would occur during that time slot. In
addition, the serializers programmed as transmitters place their data output pins in a predetermined
state (logic low, high, or high impedance) as programmed by each serializer control register (SRCTL).
Refer also to
Section 10.2.6.2
inactive time slots in TDM mode.
The receive TDM sequencer is controlled by register RTDM and reports current receive slot to RSLOT.
The transmit TDM sequencer is controlled by register XTDM and reports current transmit slot to
XSLOT.
10.2.7.5 Clock Check Circuit
A common source of error in audio systems is a serial clock failure due to instabilities in the off-chip
DIR circuit. To detect a clock error quickly, a clock-check circuit is included in the McASP for both
transmit and receive clocks, since both may be sourced from off chip.
The clock check circuit can detect and recover from transmit and receive clock failures. See
Section 10.2.8.4.6
1038
Multichannel Audio Serial Port (McASP)
Preliminary
(Section
10.2.10).
for details on how DMA event or interrupt generations are handled during
for implementation and programming details.
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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