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Architecture
19.2.10.3 Autobauding Modes
In autobauding mode, the UART extracts transfer characteristics (speed, length, and parity) from an AT
command. These characteristics are used to receive data after an "at" (AT) and to send data.
The valid AT commands follow:
AT
DATA
at
DATA
A/
a/
A line break during the acquisition of the sequence AT is not recognized, and echo functionality is not
implemented in hardware. A/ and a/ are not used to extract characteristics, but they must be recognized
because of their special meaning. Either A/ or a/ is used to instruct the software to repeat the last
received AT command; therefore, an a/ always follows an AT, and transfer characteristics are not
expected to change between an AT and an a/.
When a valid AT is received, AT and all subsequent data, including the final <CR> (0Dh), are saved to
RX FIFO. The autobaud state-machine waits for the next valid AT command. If an a/ (A/) is received,
the a/ (A/) is saved into RX FIFO and the state-machine waits for the next valid AT command.
On the first successful detection of the baud rate, the UART activates an interrupt to signify that the AT
(upper or lower case) sequence is detected. The UASR register reflects the correct settings for the
baud rate detected. The interrupt activity continues in this way each time a subsequent character is
received. Therefore, it is recommended that the software enables the RHR interrupt when using the
autobaud mode.
The following settings are detected in autobaud mode with a module clock of 48 MHz:
•
Speed: 115.2k baud, 57.6k baud, 38.4k baud, 28.8k baud, 19.2k baud, 14.4k baud, 9.6k baud, 4.8k
baud, 2.4k baud, or 1.2k baud
•
Length: 7 or 8 bits
•
Parity: Odd, even, or space
NOTE: The combination of 7-bit character + space parity is not supported.
The method used to identify the speed is:
•
Detect the transition 1->0 on the received data. This happens as soon as a stop to start bit transition
occurs. The transition is valid after a majority vote on 3 sampling period.
•
Sample the start bit duration with 115 200 × 16 Hz clock frequency as long as there is no rising
edge. A transition 0->1 is considered as valid after a majority vote on 3 sampling period.
•
Compare the sampled value with a table. If the sampled value is outside a valid range an error is
reported (no speed identified). And the hardware goes back to the first state (1).
•
Else store the first data bit in the received register (for serial to parallel conversion) and go to frame
format identification.
The next received bits are sampled according to the programmed baud rate. However, after seven bits
reception, the speed identification must be restarted since we may receive several "a" or "A" character
before a valid "t" or "T" character.
Autobauding mode is selected when the MODESELECT field in MDR1[2:0] is set to 2h. In the UART
autobauding mode, DLL, DLH, and LCR[5:0] settings are not used; instead, UASR is updated with the
configuration detected by the autobauding logic.
1712
UART/IrDA/CIR Module
Preliminary
<CR>
<CR>
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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