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Protocol Description(s)
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint
has a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets
from the FIFO without processor intervention. However, this feature is not particularly useful with
isochronous endpoints because the packets transferred are often not maximum packet size.
•
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception.
Endpoint interrupt will be generated only in the error conditions.
20.3.2.4.1.1 Isochronous IN Transfer Setup: Host
Before initiating an Isochronous IN Transactions in Host mode:
•
The target function address needs to be set in the RXFUNCADDR register for the selected
controller endpoint (RXFUNCADDR register is available for all endpoints from EP0 to EP4).
•
The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as:
– Operating speed in the SPEED bit field (bits 7 and 6).
– Set 01 (binary value) in the PROT field for isochronous transfer.
– Endpoint Number of the target device in RENDPN field. This is the endpoint number contained in
the Rx endpoint descriptor returned by the target device during enumeration.
•
The RXMAXP register for the controller endpoint must be written with the maximum packet size (in
bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard
Endpoint Descriptor for the target endpoint.
•
The HOST_RXINTERVAL register needs to be written with the required transaction interval (usually
one transaction per frame/microframe).
•
The relevant interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for
this endpoint).
•
The following bits of HOST_RXCSR register should be set as:
– Clear AUTOCLEAR
– Set the DMAEN bit (bit 13) to 1 if a DMA request is required for this endpoint.
– Clear the DISNYET it (bit 12) to 0 to allow normal PING flow control. This will only affect High
Speed transactions.
– Clear DMAMODE bit (bit 11) to 0.
•
If DMA is enabled, AUTOREQ register can be set for generating IN tokens automatically after
receiving the data. Set the bit field RXn_AUTOREQ (where n is the endpoint number) with binary
value 01 or 11.
For detailed information on using CPPI DMA, consult related section within this document.
20.3.2.4.1.2 Isochronous IN Operation: Host Mode
The operation starts with the software setting REQPKT bit of HOST_RXCSR (bit 5). This causes the
controller to send an IN token to the target.
When a packet is received, an interrupt is generated which the software may use to unload the packet
from the FIFO and clear the RXPKTRDY bit in the HOST_RXCSR register (bit 0) in the same way as
for a Bulk Rx endpoint. As the interrupt could occur almost any time within a frame(/microframe), the
timing of FIFO unload requests will probably be irregular. If the data sink for the endpoint is going to
some external hardware, it may be better to minimize the requirement for additional buffering by waiting
until the end of each frame before unloading the FIFO. This can be done by using the SOF_PULSE
signal from the controller to trigger the unloading of the data packet. The SOF_PULSE is generated
once per frame(/microframe). The interrupts may still be used to clear the RXPKTRDY bit in
HOST_RXCSR.
1792
Universal Serial Bus (USB)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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