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Architecture
10.2 Architecture
10.2.1 Overview
Figure 10-1
shows the major blocks of the McASP. The McASP has independent receive/transmit clock
generators and frame sync generators, error-checking logic, and up to 6 serial data pins. Refer to the
device-specific data manual for the number of data pins available on your device.
All the McASP pins on the device may be individually programmed as general-purpose I/O (GPIO) if
they are not used for serial port functions.
The McASP includes the following pins:
•
Serializers;
– Data pins AXRn: Up to 6 pins.
•
Transmit clock generator:
– AHCLKX: McASP transmit high-frequency master clock.
– ACLKX: McASP transmit bit clock.
•
Transmit Frame Sync Generator;
– AFSX: McASP transmit frame sync or left/right clock (LRCLK).
•
Receive clock generator;
– AHCLKR: McASP receive high-frequency master clock.
– ACLKR: McASP receive bit clock.
•
Receive Frame Sync Generator;
– AFSR: McASP receive frame sync or left/right clock (LRCLK).
•
Mute in/out;
– AMUTEIN: McASP mute input (from external device).
– AMUTE: McASP mute output.
– Data pins AXRn.
10.2.2 Clock and Frame Sync Generators
The McASP clock generators are able to produce two independent clock zones: transmit and receive
clock zones. The serial clock generators may be programmed independently for the transmit section
and the receive section, and may be completely asynchronous to each other. The serial clock (clock at
the bit rate) may be sourced:
•
Internally - by passing through two clock dividers off the internal clock source (AUXCLK).
•
Externally - directly from ACLKR/X pin.
•
Mixed - an external high-frequency clock is input to the McASP on either the AHCLKX or AHCLKR
pins, and divided down to produce the bit rate clock.
In the internal/mixed cases, the bit rate clock is generated internally and should be driven out on the
ACLKX (for transmit) or ACLKR (for receive) pins. In the internal case, an internally-generated
high-frequency clock may be driven out onto the AHCLKX or AHCLKR pins to serve as a reference
clock for other components in the system.
The McASP requires a minimum of a bit clock and a frame sync to operate, and provides the capability
to reference these clocks from an external high-frequency master clock. In DIT mode, it is possible to
use only internally-generated clocks and frame syncs. Both the AUXCLK and System Clock are
generated from SYSCLK2 (CLKDIV6 domain).
1024
Multichannel Audio Serial Port (McASP)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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