Texas Instruments TMS320C6A816 Series Technical Reference Manual page 978

C6-integra dsp+arm processors
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Registers
Table 9-23. Command and Transfer Mode Register (SD_CMD) Field Descriptions (continued)
Bit
Field
15-6
Reserved
5
MSBS
4
DDIR
3
Reserved
2
ACEN
1
BCE
0
DE
978
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
Value
Description
0
Reserved bit field. Do not write any value.
Multi/Single block select. This bit must be set to 1 for data transfer in case of multi block command.
For any others command this bit shall be cleared to 0.
0
Single block. If this bit is 0, it is not necessary to set the register SD_BLK[31:16] NBLK bits.
1
Multi block. When Block Count is disabled (SD_CMD[1] BCE bit is cleared to 0) in Multiple block
transfers (SD_CMD[5] MSBS bit is set to 1), the module can perform infinite transfer.
Data transfer Direction. Select This bit defines either data transfer will be a read or a write.
0
Data Write (host to card)
1
Data Read (card to host)
0
Reserved bit field. Do not write any value.
Auto CMD12 Enable (SD cards only). When this bit is set to 1, the host controller issues a CMD12
automatically after the transfer completion of the last block. The Host Driver shall not set this bit to
issue commands that do not require CMD12 to stop data transfer. In particular, secure commands
do not require CMD12.
For CE-ATA commands (SD_CON[12] CEATA bit set to 1), auto CMD12 is useless; therefore when
this bit is set the mechanism to detect command completion signal, named CCS, interrupt is
activated.
0
Auto CMD12 disable
1
Auto CMD12 enable or CCS detection enabled.
Block Count Enable (Multiple block transfers only). This bit is used to enable the block count
register (SD_BLK[31:16] NBLK bits). When Block Count is disabled (SD_CMD[1] BCE bit is cleared
to 0) in Multiple block transfers (SD_CMD[5] MSBS bits is set to 1), the module can perform infinite
transfer.
0
Block count disabled for infinite transfer.
1
Block count enabled for multiple block transfer with known number of blocks
DMA Enable. This bit is used to enable DMA mode for host data access.
0
DMA mode disable
1
DMA mode enable
© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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