Texas Instruments TMS320C6A816 Series Technical Reference Manual page 866

Registers
Table 7-8. I2C Status Raw Register (I2C_IRQSTATUS_RAW) Field Descriptions (continued)
Bit Field Value
2 ARDY
0
1
1 NACK
0
1
0 AL
0
1
866
Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Description
I2C mode only. This read/clear only bit, when set to 1, indicates that the previously programmed data
and command (receive or transmit, master or slave) has been performed and status bit has been
updated. The CPU uses this flag to let it know that the I2C registers are ready to be accessed again.
The CPU can only clear this bit by writing a 1 into this register. A write 0 has no effect.
Mode Others
I2C Master transmit STP = 1
I2C Master receive STP = 1
I2C Master transmit STP = 0
I2C Master receive STP = 0
I2C Master transmit -
I2C Slave receive -
No action
Access ready
Value after reset is low.
No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is
signaled to MPUSS. Write '1' to clear this bit. I2C mode only.
The read/clear only No Acknowledge flag bit is set when the hardware detects No Acknowledge has
been received. When a NACK event occurs on the bus, this bit is set to 1, the core automatically ends
the transfer and clears the MST/STP bits in the I2C_CON register and the I2C becomes a slave.
Clearing the FIFOs from remaining data might be required.
The CPU can only clear this bit by writing a 1 into this register. Writing 0 has no effect.
Normal operation
Not Acknowledge detected
Value after reset is low.
Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in
master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. I2C mode
only.
The read/clear only Arbitration Lost flag bit is set to 1 when the device (configured in master mode)
detects it has lost an arbitration (in Address Phase). This happens when two or more masters initiate a
transfer on the I2C bus almost simultaneously or when the I2C attempts to start a transfer while BB
(bus busy) is 1.
When this is set to 1 due to arbitration lost, the core automatically clears the MST/STP bits in the
I2C_CON register and the I2C becomes a slave receiver.
The CPU can only clear this bit by writing a 1 to this register. Writing 0 has no effect.
Normal operation
Arbitration lost detected
Value after reset is low.
© 2011, Texas Instruments Incorporated
ARDY Set Condition
DCOUNT = 0
DCOUNT = 0 and receiver FIFO empty
DCOUNT passed 0
DCOUNT passed 0 and receiver FIFO empty
Stop or restart condition received from master
Stop or restart condition and receiver FIFO empty
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
www.ti.com