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11.2.8.3 Data Transfer DMA Request Configuration
To configure the McBSP receive/transmit data DMA requests, perform the following procedure:
1. Write the receive THRSH1_REG register with the required receive DMA request length (the length
of the transfer is the same as the threshold value + 1). As long as the RB occupied locations level is
above or equal to the THRSH1_REG value + 1, the DMA request will be asserted. After transferring
the configured THRSH1_REG + 1 number of words, the receive DMA request (McBSP.REVNT) will
be deasserted and reasserted as soon as the conditions are met again.
Note that in case of a number of transfers that exceed the number of the programmed DMA length
the McBSP will respond to the command, and will perform the transfer regardless of the receive
buffer empty condition. When the receive buffer is empty a data transfer access will trigger a receive
underflow interrupt, if enabled by RUNDFL_EN bit in IRQENSTAT_REG register.
2. Write the transmit THRSH2_REG register with the required transmit DMA request length (the length
of the transfer is the same as the threshold value + 1). As long as the XB free locations level is
above or equal to the THRSH2_REG value + 1, the DMA request will be asserted. After transferring
the configured THRSH2_REG + 1 number of words, the transmit DMA request (McBSP.XEVNT) will
be deasserted and reasserted as soon as the conditions are met again.
Note that in case of a number of transfers that exceed the number of the programmed DMA length
the McBSP will respond to the command, and will perform the transfer regardless of the transmit
buffer full condition. When the transmit buffer is full a data transfer access will trigger a transmit
overflow interrupt, if enabled by XOVFL_EN bit in IRQENSTAT_REG register
11.2.8.4 Interrupt Configuration
The McBSP offers two interrupt schemes:
•
OCP compliant interrupt request scheme using a common receive/transmit interrupt request line .
•
The legacy interrupt compliant scheme using 3 interrupt lines: one for receive, one for transmit and
the receive overflow interrupt line.
The OCP compliant interrupt line can be configured by using the IRQENABLE register. When the
IRQSTATUS bit is set and the corresponding IRQENABLE bit is set to one, the interrupt line is
asserted. Writing one to a bit in IRQSTATUS register will clear the bit.
There are several conditions, which may be configured to generate an interrupt as follows:
•
Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which
is written while overflow condition is discarded).
•
Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new
data is required to be transmitted).
•
Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are
equal or above the (THRSH2_REG + 1) value).
•
Transmit End of Frame (XEOF is set to 1 when a complete frame was transmitted).
•
Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is
asserted).
•
Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame
synchronization error is detected).
•
Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is
written while overflow condition is discarded).
•
Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the
receive data register while receive buffer is empty; data read while underflow condition is
undefined).
•
Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations
are equal or above the (THRSH1_REG + 1) value).
•
Receive End of Frame (REOF is set to 1 when a complete frame was received).
•
Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is
asserted).
•
Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame
synchronization error is detected).
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
Architecture
1157
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