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Protocol Description(s)
pull-up resistor to signify the external host that it is a Full-Speed device. Note that even when operating
as a High-Speed peripheral; the USB controller has to first come up as Full-Speed and then later
transition to High-Speed. The USB2.0 controller will then waits for a reset bus condition from the
external host. Then after, if High-Speed option has been selected it will negotiate for a High-Speed
operation and if its request has been accepted by the host, it will enable its precision 45ohm resistors
on its data lines and disable the 1.5Kohm resistor.
20.3 Protocol Description(s)
This section describes the implementation of the USB protocol(s) by the USB modules.
20.3.1 USB Controller Peripheral Mode Operation
The USB controller assumes the role of a peripheral when the USB Mode Register[iddig=bit8] is set to
1 by the user application prior to the controller goes into session. When the USB controller go into
session it will assume the role of a device.
Soft connect –After a POR or USB Module soft reset, the SOFTCONN bit of POWER register (bit 6) is
cleared to 0. The controller will therefore appear disconnected until the software has set the
SOFTCONN bit to 1. The application software can then choose when to set the PHY into its normal
mode. Systems with a lengthy initialization procedure may use this to ensure that initialization is
complete and the system is ready to perform enumeration before connecting to the USB. Once the
SOFTCONN bit has been set, the software can also simulate a disconnect by clearing this bit to 0.
Entry into suspend mode –When operating as a peripheral device, the controller monitors activity on the
bus and when no activity has occurred for 3 ms, it goes into Suspend mode. If the Suspend interrupt
has been enabled, an interrupt will be generated at this time.
At this point, the controller can then be left active (and hence able to detect when Resume signaling
occurs on the USB), or the application may arrange to disable the controller by stopping its clock.
However, the controller will not then be able to detect Resume signaling on the USB if clocks are not
running. If such is the case, external hardware will be needed to detect Resume signaling (by
monitoring the DM and DP signals), so that the clock to the controller can be restarted.
Resume Signaling –When resume signaling occurs on the bus, first the clock to the controller must be
restarted if necessary. Then the controller will automatically exit Suspend mode. If the Resume interrupt
is enabled, an interrupt will be generated.
Initiating a remote wakeup –If the software wants to initiate a remote wakeup while the controller is in
Suspend mode, it should set the POWER[RESUME] bit to 1. The software should leave then this bit set
for approximately 10 ms (minimum of 2 ms, a maximum of 15 ms) before resetting it to 0.
NOTE: No resume interrupt will be generated when the software initiates a remote wakeup.
Reset Signaling –When reset signaling or bus condition occurs on the bus, the controller performs the
following actions:
•
Clears FADDR register to 0
•
Clears INDEX register to 0
•
Flushes all endpoint FIFOs
•
Clears all controller control/status registers
•
Generates a reset interrupt
•
Enables all interrupts at the core level.
If the HSENA bit within the POWER register (bit 5) is set, the controller also tries to negotiate for
high-speed operation. Whether high-speed operation is selected is indicated by HSMODE bit of
POWER register (bit 4). When the application software receives a reset interrupt, it should close any
open pipes and wait for bus enumeration to begin.
1760
Universal Serial Bus (USB)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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