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Architecture
12.2.3.3 Master Transmit and Receive Mode
This mode is programmable per channel (bits TRM of the register (I)CONF).
The channel access to the shift registers, for transmission/reception, is based on its transmitter and
receiver register state and round robin arbitration.
The channel that meets the rules below is included in the round robin list of already active channels
scheduled for transmission and/or reception. The arbiter skips the channel that does not meet the rules
and search for the next following enabled channel, in rotation.
Rule 1: Only enabled channels (bit EN of the register MCSPI_CH(I)CTRL), can be scheduled for
transmission and/or reception.
Rule 2: An enabled channel can be scheduled if its transmitter register is not empty (bit TXS of the
register MCSPI_CH(I)STAT) or its FIFO is not empty in case of buffer use for the corresponding
channel (bit FFE of the register MCSPI_CH(I)STAT), that is updated with new data, at the time of shift
register assignment. If the transmitter register or FIFO is empty, at the time of shift register assignment,
the event TX_underflow is activated and the next enabled channel with new data to transmit is
scheduled. (See also transmit only mode).
Rule 3: An enabled channel can be scheduled if its receive register is not full (bit RXS of the register
MCSPI_CH(I)STAT) ) or its FIFO is not full in case of buffer use for the corresponding channel (bit FFF
of the register MCSPI_CH(I)STAT) at the time of shift register assignment. (See also receive only
mode). Therefore the receiver register of FIFO cannot be overwritten. The RX_overflow bit, in the
MCSPI_IRQSTATUS register is never set in this mode.
On completion of SPI word transfer (bit EOT of the register MCSPI_CH(I)STAT is set) the updated
transmitter register of the next scheduled channel is loaded into the shift register. This bit is
meaningless when using the Buffer for this channel. The serialization (transmit and receive) starts
according to the channel communication configuration. On serialization completion the received data is
transferred to the channel receive register.
The built-in FIFO is available in this mode and can be configured in one data direction Transmit or
Receive, then the FIFO is seen as a unique FFNBYTE bytes buffer, or it can also be configured in both
data direction Transmit and Receive, then the FIFO is split into two separate FFNBYTE/2 bytes buffer
with their own address space management, in this last case the definition of AEL and AFL levels is
based on FFNBYTE/2 bytes and is under CPU responsibility.
12.2.3.4 Master Transmit-Only Mode
This mode avoids the CPU to read the receiver register (minimizing data movement) when only
transmission is meaningful.
The master transmit only mode is programmable per channel (bits TRM of the register (I)CONF).
In master transmit only mode, transmission starts after data is loaded into the transmitter register.
Rule 1 and Rule 2, defined above, are applicable in this mode.
Rule 3, defined above, is not applicable: In master transmit only mode, the receiver register or FIFO
state "full" does not prevent transmission, and the receiver register is always overwritten with the new
SPI word. This event in the receiver register is not significant when only transmission is meaningful. So,
the RX_overflow bit, in the MCSPI_IRQSTATUS register is never set in this mode.
The McSPI module automatically disables the RX_full interrupt status. The corresponding interrupt
request and DMA Read request are not generated in master transmit only mode.
The status of the serialization completion is given by the bit EOT of the register MCSPI_CH(I)STAT.
This bit is meaningless when using the Buffer for this channel.
The built-in FIFO is available in this mode and can be configured with FFEW bit field in the
MCSPI_CH(I)CONF register, then the FIFO is seen as a unique FFNBYTE bytes buffer.
1224
Multichannel Serial Port Interface (McSPI)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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