Texas Instruments TMS320C6A816 Series Technical Reference Manual page 992

Registers
Table 9-32. Interrupt Status Register (SD_STAT) Field Descriptions (continued)
Bit Field
18 CEB
17 CCRC
16 CTO
15 ERRI
14-11 Reserved
10 BSR
9 OBI
992
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
Value Description
Command end bit error. This bit is set automatically when detecting a 0 at the end bit position
of a command response.
Read 0 No error
Write 0 Status bit unchanged
Read 1 Command end bit error
Write 1 Status is cleared.
Command CRC error. This bit is set automatically when there is a CRC7 error in the
command response depending on the enable bit (SD_CMD[19] CCCE).
Read 0 No error
Write 0 Status bit unchanged
Read 1 Command CRC error
Write 1 Status is cleared.
Command timeout error. This bit is set automatically when no response is received within 64
clock cycles from the end bit of the command.
For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles.
Read 0 No error
Write 0 Status bit unchanged
Read 1 Time Out
Write 1 Status is cleared.
Error interrupt. If any of the bits in the Error Interrupt Status register (SD_STAT[31:16]) are
set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by
checking this bit first.
Writes to this bit are ignored.
Read 0 No interrupt
Read 1 Error interrupt event(s) occurred
0 Reserved bit field. Do not write any value
Boot Status Received Interrupt. This bit is set automatically when SD_CON[BOOT] is set 1 or
2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card.
Read 0 No interrupt
Write 0 Status bit unchanged
Read 1 Boot Status Received Interrupt occurred.
Write 1 Status is cleared.
Out-of-band interrupt (This interrupt is only useful for MMC card). This bit is set automatically
when SD_CON[14] OBIE bit is set and an out-of-band interrupt occurs on OBI pin.
The interrupt detection depends on polarity controlled by SD_CON[13] OBIP bit.
The out-of-band interrupt signal is a system specific feature for future use, this signal is not
required for existing specification implementation.
Read 0 No out-of-band interrupt
Write 0 Status bit unchanged
Read 1 Interrupt out-of-band occurs
Write 1 Status is cleared.
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SPRUGX9 – 15 April 2011
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