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Basic Programming Model
8.3
Basic Programming Model
8.3.1 Initialization Sequence
1. Program the INTCPS_SYSCONFIG register: If necessary, enable the interface clock autogating by
setting the AUTOIDLE bit.
2. Program the INTCPS_IDLE register: If necessary, disable functional clock autogating or enable
synchronizer autogating by setting the FUNCIDLE bit or TURBO bit accordingly.
3. Program the INTCPS_ILRm register for each interrupt line: Assign a priority level and set the
FIQNIRQ bit for an FIQ interrupt (by default, interrupts are mapped to IRQ and priority is 0
[highest]).
4. Program the INTCPS_MIRn register: Enable interrupts (by default, all interrupt lines are masked).
To program the INTCPS_MIRn register, the INTCPS_MIR_SETn and INTCPS_MIR_CLEARn
registers are provided to facilitate the masking, even if it is possible for backward-compatibility to
write directly to the INTCPS_MIRn register.
8.3.2 INTC Processing Sequence
After the INTCPS_MIRn and INTCPS_ILRm registers are configured to enable and assign priorities to
incoming interrupts, the interrupt is processed as explained in the following subsections. IRQ and FIQ
processing sequences are quite similar, the differences for the FIQ sequence are shown after a '/'
character in the code below.
1. One or more unmasked incoming interrupts (M_IRQ_n signals) are received and IRQ or FIQ outputs
(IRQ/FIQ) are not currently asserted.
2. If the INTCPS_ILRm[0] FIQNIRQ bit is cleared to 0, the MPU_INTC_IRQ output signal is generated.
If the FIQNIRQ bit is set to 1, the MPU_INTC_FIQ output signal is generated.
3. The INTC performs the priority sorting and updates the INTCPS_SIR_IRQ[6:0] ACTIVEIRQ
/INTCPS_SIR_FIQ[6:0] ACTIVEFIQ field with the current interrupt number.
4. During priority sorting, if the IRQ/FIQ is enabled at the host processor side, the host processor
automatically saves the current context and executes the ISR as follows.
The ARM host processor automatically performs the following actions in pseudo code:
LR = PC + 4
SPSR = CPSR
CPSR[5] = 0
CPSR[7] = 1
CPSR[8] = 1
CPSR[9] = CP15_reg1_EEbit
if interrupt == IRQ then
CPSR[4:0] = 0b10010
if high vectors configured then
PC = 0xFFFF0018
else
PC = 0x00000018
else if interrupt == FIQ then
CPSR[4:0] = 0b10001
CPSR[6] = 1
if high vectors configured then
PC = 0xFFFF001C
else
PC = 0x0000001C
endif
908
Interrupt Controller
Preliminary
/* return link */
/* Save CPSR before execution */
/* Execute in ARM state */
/* Disable IRQ */
/* Disable Imprecise Data Aborts */
/* Endianness on exception entry */
/* Enter IRQ mode */
/* execute interrupt vector */
/* Enter FIQ mode */
/* Disable FIQ */
/* execute interrupt vector */
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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