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Architecture
12.2.4.2.2 TX_UNDERFLOW
The event TX_underflow is activated when channel is enabled and if the transmitter register or FIFO (if
use of buffer is enabled) is empty (not updated with new data) when an external master device starts a
data transfer with McSPI (transmit and receive).
When FIFO is enabled the data emitted while underflow event is raised is not the last data written in the
FIFO.
The TX_underflow indicates an error (data loss) in slave mode.
To avoid having TX_underflow event at the beginning of a transmission, the event TX_underflow is not
activated when no data has been loaded into the transmitter register since channel has been enabled.
TX_underflow interrupt status bit must be cleared for interrupt line de-assertion (if event enable as
interrupt source).
12.2.4.2.3 RX_FULL
The event RX_full is activated when channel is enabled and receiver becomes filled (transient event).
When FIFO buffer is enabled (MCSPI_CH(I)CONF[FFER] set to 1), the RX_full is asserted as soon as
there is a number of bytes holds in buffer to read defined by MCSPI_XFERLEVEL[AFL].
Receiver register must be read to remove source of interrupt and RX_full interrupt status bit must be
cleared for interrupt line de-assertion (if event enable as interrupt source).
When FIFO is enabled, no new RX_full event will be asserted as soon as Local Host has not performed
the number of read into receive register defined by MCSPI_XFERLEVEL[AFL]. It is the responsibility of
Local Host to perform the right number of reads.
12.2.4.2.4 RX_OVERFLOW
The RX0_OVERFLOW event is activated in slave mode in either transmit-and-receive or receive-only
mode, when a channel is enabled and the SPI_RXn register or FIFO is full when a new SPI word is
received. The SPI_RXn register is always overwritten with the new SPI word. If the FIFO is enabled
data within the FIFO are overwritten, it must be considered as corrupted. The RX0_OVERFLOW event
should not appear in slave mode using the FIFO.
The RX0_OVERFLOW indicates an error (data loss) in slave mode.
The SPI_IRQSTATUS[3] RX0_OVERFLOW interrupt status bit must be cleared for interrupt line
deassertion (if the event is enabled as the interrupt source).
12.2.4.2.5 End of Word Count
The event EOW (End Of Word count) is activated when channel is enabled and configured to use the
built-in FIFO. This interrupt is raised when the controller had performed the number of transfer defined
in MCSPI_XFERLEVEL[WCNT] register. If the value was programmed to 0000h, the counter is not
enabled and this interrupt is not generated.
The End of Word count interrupt also indicates that the SPI transfer is halt on channel using the FIFO
buffer as soon as MCSPI_XFERLEVEL[WCNT] is not reloaded and channel re-enabled.
End of Word interrupt status bit must be cleared for interrupt line de-assertion (if event enable as
interrupt source).
12.2.4.3 Slave Transmit-and-Receive Mode
The slave transmit and receive mode is programmable (bits TRM cleared to 0 in the register
MCSPI_CH(I)CONF).
After the channel is enabled, transmission and reception proceed with interrupt and DMA request
events.
In slave transmit and receive mode, transmitter register should be loaded before McSPI is selected by
an external SPI master device.
1242
Multichannel Serial Port Interface (McSPI)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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