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For left-aligned Q31 data, the following transmit format unit settings process the data into right aligned
24-bit audio data ready for transmission:
•
XROT = 010 (rotate right by 8 bits).
•
XRVRS = 0 (no bit reversal, LSB first).
•
XMASK = FFFF FF00h-FFFF 0000h (depending upon whether 24, 23, 22, 21, 20, 19, 18, 17, or 16
valid audio data bits are present).
•
XPAD = 00 (pad extra bits with 0).
For right-aligned data, the following transmit format unit settings process the data into right aligned
24-bit audio data ready for transmission:
•
XROT = 000 (rotate right by 0 bits).
•
XRVRS = 0 (no bit reversal, LSB first).
•
XMASK = 00FF FFFFh to 0000 FFFFh (depending upon whether 24, 23, 22, 21, 20, 19, 18, 17, or
16 valid audio data bits are present).
•
XPAD = 00 (pad extra bits with 0).
10.2.6.3.2 Transmit DIT Clock and Frame Sync Generation
The DIT transmitter only works in the following configuration:
•
In transmit frame control register (AFSXCTL):
– Internally-generated transmit frame sync, FSXM = 1.
– Rising-edge frame sync, FSXP = 0.
– Bit-width frame sync, FXWID = 0.
– 384-slot TDM, XMOD = 1 1000 0000b.
•
In transmit clock control register (ACLKXCTL), ASYNC = 1.
•
In transmit bitstream format register (XFMT), XSSZ = 1111 (32-bit slot size).
All combinations of AHCLKX and ACLKX are supported.
This is a summary of the register configurations required for DIT mode. The DIT mode specific bit fields
are in bold face:
•
PFUNC: The data pins must be configured for McASP function. If AHCLKX is used, it must also be
configured for McASP function.
•
PDIR: The data pins must be configured as outputs. If AHCLKX is used as an input reference, it
should be configured as input. If internal clock source AUXCLK is used as the reference clock, it
may be output on the AHCLKX pin by configuring AHCLKX as an output.
•
PDOUT, PDIN, PDSET, PDCLR: Not applicable for DIT operation. Leave at default.
•
GBLCTL: Follow the initialization sequence in
•
AMUTE: Program all fields according to mute control desired.
•
DLBCTL: Not applicable. Loopback is not supported for DIT mode. Leave at default.
•
DITCTL: DITEN bit must be set to 1 to enable DIT mode. Configure other bits as desired.
•
RMASK: Not applicable. Leave at default.
•
RFMT: Not applicable. Leave at default.
•
AFSRCTL: Not applicable. Leave at default.
•
ACLKRCTL: Not applicable. Leave at default.
•
AHCLKRCTL: Not applicable. Leave at default.
•
RTDM: Not applicable. Leave at default.
•
RINTCTL: Not applicable. Leave at default.
•
RCLKCHK: Not applicable. Leave at default.
•
XMASK: Mask desired bits according to the discussion in this section, depending upon left-aligned
or right-aligned internal data.
•
XFMT: XDATDLY = 0. XRVRS = 0. XPAD = 0. XPBIT = default (not applicable). XSSZ = Fh (32-bit
slot). XBUSEL = configured as desired. XROT bit is configured according to the discussion in this
section, either 0 or 8-bit rotate.
SPRUGX9 – 15 April 2011
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Preliminary
Section 10.2.10.2
© 2011, Texas Instruments Incorporated
to configure this register.
Multichannel Audio Serial Port (McASP)
Architecture
1033
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