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Protocol Description(s)
20.3.2.1.4 Status Phase (Status for OUT Data Phase or Setup Phase) of a Control Transaction: Host
Mode
IN Status Phase of a control transfer exists for a Zero Data Request or for a Write Request of a control
transfer. The IN Status Phase follows the Setup Stage, if no Data Stage of a control transfer exists, or
OUT Data Phase of a Data Stage of a control transfer.
For the IN Status Phase of a control transaction
device needs to:
1. Set the STATUSPKT and REQPKT bits of HOST_CSR0 (bit 6 and bit 5, respectively).
2. Wait while the controller sends an IN token and receives a response from the USB peripheral
device.
3. When the controller generates the Endpoint 0 interrupt, read HOST_CSR0 to establish whether the
RXSTALL bit (bit 2), the ERROR bit (bit 4), the NAK_TIMEOUT bit (bit 7) or RXPKTRDY bit (bit 0)
has been set.
If RXSTALL bit is set, it indicates that the target could not complete the command and so has issued
a STALL response.
If ERROR bit is set, it means that the controller has tried to send the required IN token three times
without getting any response.
If NAK_TIMEOUT bit is set, it means that the controller has received a NAK response to each
attempt to send the IN token, for longer than the time set in the HOST_NAKLIMIT0 register. The
controller can then be directed either to continue trying this transaction (until it times out again) by
clearing the NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT bit and
STATUSPKT bit before clearing the NAK_TIMEOUT bit.
4. The CPU should clear the STATUSPPKT bit of HOST_CSR0 together with (i.e., in the same write
operation as) RxPktRdy if this has been set.
1784
Universal Serial Bus (USB)
Preliminary
(Figure
20-10), the software driving the USB Host
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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