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12.2.8 Power Saving Management
Independently of the module operational modes (Transmit and/or Receive), two modes of operations
are defined from a power management perspective: normal and idle modes.
The two modes are temporally fully exclusive.
McSPI is compliant with the profile "IdleReq / SIdleAck / Swakup" in the Idle mode defined in reference
[4].
12.2.8.1 Normal Mode
Both the OCP clock and SPI clock (CLKSPIREF) provided to McSPI must be active for both master and
slave modes. The auto-gating of the module OCP clock and SPI clock occurs when the following
conditions are met:
•
The bit AutoIdle of the register MCSPI_SYSCONFIG is set.
•
In master mode, there is no data to transmit or receive in all channels.
•
In slave mode, the SPI is not selected by the external SPI master device and no OCP accesses.
Autogating of the module OCP clock and SPI clock stops when the following conditions are met:
•
In master mode, an OCP access occurs.
•
In slave mode, an OCP access occurs or McSPI is selected by an external SPI master device.
12.2.8.2 Idle Mode
The OCP clock and SPI clock provided to McSPI may be switched off on system power manager
request and switched back on module request.
McSPI is compliant with the power management handshaking protocol: idle request from the system
power manager, idle acknowledgement from McSPI.
The idle acknowledgement in response to an idle request from the system power manager varies
according to a programmable mode in the MCSPI_SYSCONFIG register: No idle mode, force idle
mode, and smart idle mode.
•
When programmed for no idle mode (the bit SIdleMode of the register MCSPI_SYSCONFIG is set
to "01"), the module ignores the system power manager request, and behaves normally, as if the
request was not asserted.
•
When programmed for smart idle mode (the bit SIdleMode of the register MCSPI_SYSCONFIG is
set to "10"), the module acknowledges the system power manager request according to its internal
state.
•
When programmed for force idle mode (the bit SIdleMode of the register MCSPI_SYSCONFIG is
set to "00"), the module acknowledges the system power manager request unconditionally.
The OCP clock will be optionally switched off, during the smart idle mode period, if the bit ClockActivity
of the register MCSPI_SYSCONFIG is set.
The SPI clock will be optionally switched off, during the smart idle mode period, if the second bit
ClockActivity of the register MCSPI_SYSCONFIG is set.
McSPI assumes that both clocks may be switched off whatever the value set in the field ClockActivity of
the register MCSPI_SYSCONFIG.
12.2.8.2.1 Transitions from Normal Mode to Smart-Idle Mode
The module detects an idle request when the synchronous signal IdleReq is asserted.
When IdleReq is asserted, any access to the module will generate an error as long as the OCP clock is
alive.
When configured as a slave device, McSPI responds to the idle request by asserting the SIdleAck
signal (idle acknowledgement) only after completion of the current transfer (SPIEN slave selection
signal deasserted by the external master) and if interrupt or DMA request lines are not asserted.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Multichannel Serial Port Interface (McSPI)
Architecture
1247
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