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19.2.7 Interrupts
The UART/IrDA/CIR module generates interrupts. All interrupts can be enabled/disabled by writing to
the appropriate bit in the interrupt enable register (IER). The interrupt status of the device can be
checked at any time by reading the interrupt identification register (IIR). The UART, IrDA and CIR
modes have different interrupts in the UART/IrDA/CIR module and therefore different IER and IIR
mappings according to the selected mode.
19.2.7.1 Trigger Levels
The UART provides programmable trigger levels for both receiver and transmitter DMA and Interrupt
generation. After reset, both transmitter and receiver FIFOs are disabled; so, in effect, the trigger level
is the default value of one byte. The programmable trigger levels are an enhanced feature available via
the trigger level register (TLR).
19.2.7.2 UART Mode Interrupts
In UART modes, there are seven possible interrupts. These interrupts are prioritized to six different
levels. When an interrupt is generated, the interrupt identification register (IIR) indicates that an
interrupt is pending by bringing IIR[0] to 0 and provides the type of interrupt through IIR[5-1].
summarizes the interrupt control functions.
It is important to note that for the receiver line status interrupt, RX_FIFO_STS bit (LSR[7]) generates
the interrupt. For the XOFF interrupt, if a XOFF flow character detection caused the interrupt, the
interrupt is cleared by a XON flow character detection. If special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
IIR[5:0]
Priority Level
00 0001
None
00 0110
1
00 1100
2
00 0100
2
00 0010
3
00 0000
4
01 0000
5
10 0000
6
SPRUGX9 – 15 April 2011
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Preliminary
Table 19-4. UART Mode Interrupts
Interrupt Type
Interrupt Source
None
None
Receiver line
OE, FE, PE, or BI errors occur in
status
characters in the RX FIFO.
RX time-out
Stale data in RX FIFO
RHR interrupt
DRDY (data ready) (FIFO disable)
RX FIFO above trigger level (FIFO
enable)
THR interrupt
TFE (THR empty) (FIFO disable)
TX FIFO below trigger level (FIFO
enable)
Modem status
See the MSR register.
XOFF
Receive XOFF characters/special
interrupt/special
character
character
interrupt
CTS, RTS, DSR RTS pin, CTS pin, or DSR pin
changes state from active (low) to
inactive (high).
© 2011, Texas Instruments Incorporated
Architecture
Table 19-4
Interrupt Reset Method
None
FE, PE, BI: Read RHR register. OE:
Read LSR register.
Read RHR register.
Read RHR register until interrupt
condition disappears.
Write to THR register until interrupt
condition disappears.
Read MSR register.
Receive XON character(s), if XOFF
interrupt. Read IIR register, if special
character interrupt.
Read IIR register.
UART/IrDA/CIR Module
1707
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