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20.1.5.4 USB PHY
The USB subsystem is made of two USB modules. Each USB module comprises a Synopsys
Designware core USB 2.0 PHY. The PHY is connected to the USB controller via 8-bit UTMI Interface.
The PHY does not have a built-in charge pump and an external power source is required to source the
5V VBUS power when operating as a Host.
20.1.5.5 USB Pads
The USB subsystem external interface signals comprises two differential data lines, two Voltage Buses
(VBUS), and two USB DRVVBUS signals (enable/disable external 5V Power Source). No USB ID pad
exists. The Register field that is user software controlled is used as a replacement for the ID pad usage.
For more details about the USB0 and USB1 mode registers, see
Section
20.9.2.2.22, respectively.
20.1.5.6 DMA Resources
The CPPI DMA alongside with the Queue Manager and the Scheduler are used to perform data
transfer for Endpoints 1 to 15.
20.1.5.7 Interrupts
There are three interrupt interfaces: one for the USB subsystem, one for the USB0 controller, and one
for the USB1 controller. All interrupts for that specific unit are aggregated into one interrupt interface.
Each interrupt has two basic registers: STATUS and ENABLE. Hardware can set the register via
internal logic. Software can set or clear the register by accessing the appropriate locations in the
memory map. The enabling (or masking) of the interrupt is controlled via software. Writing 1's (WR1) to
either the IRQENABLE_SET or IRQENABLE_CLR addresses will enable or disable the interrupt
respectively. An EOI function exists to re-enable the detection of active interrupts. If the system
attempts to write to any of the interrupt registers, any still active interrupts will trigger the EOI output
signal. The EOI input signal indicates when external logic requires the USB to re-evaluate its pending
sources and send another pulse. For more information see section "Interrupt Support."
Note: When generating an interrupt by writing to one of the IRQ_ENABLE_SET registers; the interrupt
can occur several cycles before the OCP write status complete has occurred.
20.1.6 Supported Use Case(s)
The USB subsystem supports two USB OTG modules that are capable of operating as a mini-host and
device. OTG features are not supported.
20.1.7 Industry Standard(s) Compliance
The USB subsystem complies with the following standards:
•
Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the On-The-Go
supplement to the USB 2.0 Specification. However it does not support OTG functionality.
20.1.8 Non-Industry Standard(s)
The USB subsystem complies with the following proprietary standards:
•
Mentor Dual Role Controller (MUSBMHDRC) – USB Controller
•
SR70LX – Physical Layer: Synopsys DesignWare Core USB 2.0 nanoPHY
•
TI CPPI 4.1 – Built in 1st party DMA and Structure
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Section 20.9.2.1.22
and
Universal Serial Bus (USB)
Introduction
1755
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