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Architecture
19.2.6.2 FIFO Polled Mode Operation
In FIFO polled mode (FCR[0] = 0, relevant interrupts disabled via interrupt enable register (IER)) the
status of the receiver and transmitter can then be checked by polling the line status register (LSR). This
mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and
transmitter is automatically known by means of interrupts sent to the LH.
19.2.6.3 FIFO DMA Mode Operation
19.2.6.3.1 DMA Signaling
There are four modes of DMA operation, DMA mode 0/1/2/3. They can be selected as follows:
•
When SCR[0] = 0: setting FCR[3] to 0 enables DMA mode 0, setting FCR[3] to 1 enables DMA
mode 1.
•
When SCR[0] = 1: SCR[2:1] determines DMA mode 0 to 3, according to supplementary control
register (SCR).
So for instance:
•
if no DMA operation is desired: set SCR[0] to 1 and SCR[2:1] to 00 (FCR[3] is discarded)
•
if DMA mode 1 is desired: either set SCR[0] to 0 and FCR[3] to 1 or set SCR[0] to 1 and SCR[2:1]
to 01 (FCR[3] is discarded)
If the FIFOs are disabled (FCR[0] = 0), DMA occurs in single character transfers.
NOTE:
Note that when DMA mode 0 has been programmed, the signals associated with DMA
operation are not active.
19.2.6.3.2 DMA Transfers (DMA Mode 1, 2, or 3)
Figure
19-21,
Figure
In receive mode, a DMA request is generated as soon as the receive FIFO reaches its threshold level
defined in the trigger level register (TLR). This request is de-asserted when the number of bytes
defined by the threshold level has been read by the system DMA.
In transmit mode, a DMA request is automatically asserted when the transmit FIFO is empty. This
request is de-asserted when the number of bytes defined by the number of spaces in the trigger level
register (TLR) has been written by the system DMA. If an insufficient number of characters are written,
then the DMA request will remain active.
The DMA request is again asserted if the FIFO can receive the number of bytes defined by the TLR
register.
There are a number of ways the threshold can be programmed. The example in
DMA transfer that operates with a space setting of 56, which could arise from the use of the auto
settings in the FCR[5:4] or the use of the TLR[3:0] concatenated with the FCR[5:4]. The setting of 56
spaces in the UART/IrDA/CIR module should correlate with settings of the system DMA so that the
buffer does not overflow (program the DMA request size of the Local Host controller to be equal to the
number of spaces value in the UART/IrDA/CIR module).
1702
UART/IrDA/CIR Module
Preliminary
19-22,
Figure
19-23, and
© 2011, Texas Instruments Incorporated
Figure 19-24
show the supported DMA operations.
www.ti.com
Figure 19-22
is of a
SPRUGX9 – 15 April 2011
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