Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1629

www.ti.com
Table 16-37. Port PHY Control Register (P#PHYCR) Field Descriptions (continued)
Bit Field
6-5 LB
4-1 MPY
0 ENPLL
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Value Description
Loopback. Enables Loopback.
Note: This field applies to Port 0 only, P0PHYCR. This bit is reserved for Port 1, P1PHYCR.
0 Disabled.
1h Reserved.
2h Inner loopback, CML driver disabled. The loopback path is fully digital and excludes the transmit
CML driver and receive sense amps. The transmit CML driver is disabled.
3h Inner loopback, CML driver enabled. As above, but the CML driver operates normally.
0-Fh PLL Multiply. Select PLL multiply factors between 5 and 20.
The MPY factor along with the SERDES_CLKP/N frequency is what determines the required data
rate. Full Rate corresponds to 3Gbps Line Rate (Gen2) and Half Rate corresponds to 1.5Gbps Line
Rate (Gen1).
Example: If SERDES_CLKP/N is300MHz, then MPY=4'b0001 (5x).
Note: This field should only be written before or at the same time while enabling the ENPLL field.
You should not change MPY field after the PLL is enabled.
Note: This field applies to Port 0 only, P0PHYCR. This field is reserved for Port 1, P1PHYCR.
0 4x
1h 5x
2h 6x
3h 8x
4h 8.25x
5h 10x
6h 12x
7h 12.5x
8h 15x
9h 16x
Ah 16.5x
Bh 20x
Ch 22x
Dh 25x
Eh Reserved.
Fh Reserved.
Enable PHY PLL. This bit must be written to 1 to enable the PHY's PLL and use the link.
Note: This must be enabled by software before initialization is started on the device.
Note: This bit should not be enabled unless the MPY field has been previously set or is being set in
the same write. Changing the MPY field while the PLL is enabled disrupts the link clocks and may
disrupt the link, requiring a port reset to fix.
Note: This field applies to Port 0 only, P0PHYCR. This bit is reserved for Port 1, P1PHYCR.
0 Disabled.
1 Enabled.
© 2011, Texas Instruments Incorporated
Registers
Serial ATA (SATA) Controller
1629