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16.2.13 Interrupt Support
The AHCI controller supports both standard interrupt sourcing, where interrupts are generated when
enabled events occur, or a different type of method of generating interrupts that minimize interrupt
loading by either generating interrupts in a batch or periodically. The latter method is handled using
Command Completion Coalescing method and the details is captured within the AHCI Specification
Version 1.1.
16.2.13.1 Command Completion Coalescing
Command Completion Coalescing (CCC) is a feature designed to reduce the interrupt and command
completion overhead in a heavily loaded system. The feature enables the number of interrupts taken
per completion to be reduced significantly, while ensuring a minimum quality of service for command
completions. When software specified number of commands have completed or a software specified
timeout has expired, an interrupt is generated by hardware to allow software to process completed
commands. The command completion coalescing ports register (CCC_PORTS) should be programmed
by setting the corresponding bit of the Port that is to be included in command completion coalescing
feature. Note that the device supports 2 HBA ports.
For a detailed explanation of the CCC initialization and usage, see the AHCI Specification 1.1
Section 11.6.
16.2.13.1.1 CCC Interrupt Based on Timer Expiration
When CCC is enabled and the desired method to receive an interrupt is based on a timer elapse
condition, then the user needs to communicate a resolution for a 1ms time by programming the
TIMER1MS register with the OCP cycle count derived from the OCP clock frequency sourced to the
SATA controller.
As an example, if a user desires for interrupt to be generated every 15ms, for OCP bus Clock
frequency of 250 MHz, the 1ms cycle count should be programmed with a value of 250,000, i.e. 250
MHz/1000 = 250000d, and CCC_CTL.TV is programmed with a non-Zero value (15 in this case). When
CCC_CTL.EN is set to 1 (CCC is enabled), the CCC will periodically generate interrupt every 15 ms or
every15 * 250000 = 3,750,000 OCP cycles.
NOTE: Make sure the EN bit in the command completion coalescing control register (CCC_CTL)
is cleared to 0 (i.e., CCC is disabled, prior to programming this field).
16.2.13.1.2 CCC Interrupt Based on Completion Count
When CCC is enabled and the desired method to receive an interrupt is based on a completion count,
that is, the CC bit in the command completion coalescing control register (CCC_CTL) is programmed
with a non-zero value and the CCC interrupt is enabled (EN bit in CCC_CTL is set to 1), an interrupt is
sourced from the SATA controller when the programmed desired number of interrupt is received.
NOTE: Make sure the EN bit in the command completion coalescing control register (CCC_CTL)
is cleared to 0 (i.e., CCC is disabled, prior to programming this field).
16.2.13.2 Non CCC Interrupt Configuration
For a standard interrupt handling method where every event that is enabled generates an interrupt, is
handled as follows. For more information, see the AHCI Specification.
After insuring that CCC is disabled, the EN bit in the command completion coalescing control register
(CCC_CTL) is 0, in order for the SATA Core to source interrupts, the interrupt should be enabled at
both global level (the IE bit in the global HBA control register (GHC) is set to 1) and port level by
enabling the bit fields for the desired interrupt. An enable bit at a Port level controls corresponding
interrupt dispatch to the processor interrupt handling resource. So long as the CPU interrupt handler is
configured properly, the CPU receives the interrupt when the enabled event occurs.
SPRUGX9 – 15 April 2011
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© 2011, Texas Instruments Incorporated
Architecture
Serial ATA (SATA) Controller
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