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Architecture
Note that the BAR Mask Registers are accessible, for configuration purposes of the BARs, only when
operating as EP and at the same time only when CMD_STATUS[DBI_CS2] is set/ enabled. Firmware
needs to always read back the data written after modification to ensure that the write has completed
since the confirmation read will not happen until the write completion insuring the register update is
made prior to use. Firmware needs to clear CMD_STATUS[DBI_CS2] after initial configuration prior to
RC starts enumeration.
It is important to not attempt modification of BAR Mask Registers from serial link side as unpredictable
behavior may occur and the system could become unstable and even worse unusable.
13.2.3.3 Address Alignment Requirement
As per PCIe standard, no transaction can cross a 4 KB-aligned address boundary. The limit on
transaction size on the internal bus interface (OCP) is 128 bytes. So, the transactions must be 128 byte
or smaller on the internal bus interface. If a transaction received in inbound direction crosses a 128 byte
aligned address, then the PCIESS master interface can split such transaction into multiple transactions
at the 128 byte boundary.
13.2.3.4 Byte Strobe Usage Requirements
For any type of write transactions, the byte enables can only have a single unbroken string of 1s. In
other words, in a transaction, if a byte's write strobe is set, then all following bytes must have write
strobe set until the last byte with write enabled. "Holes" or "Zeros" in between the byte enables are not
allowed.
Since the internal bus width is greater that 32-bit, the TLP size will not be 1 (PCIe counts in 32-bit units)
and therefore, it is through the FBE/LBE (First/Last Byte Enable) that the actual data transfer size is
controlled.
13.2.3.5 Zero-Length Read/Write Transactions
Read transactions that request zero bytes are not supported by PCIESS. PCIESS will read issue a read
with FBE field of PCIe TLP set to Fh. Writes of zero bytes are supported.
13.2.3.6 Transactions Crossing 4KB Boundary
Any single transaction that reads/writes data on locations crossing a 4KB aligned address are invalid as
per PCIe Standard Section 2.2.7. If such a read is issued to PCIESS Slave, it will lead to two
transactions on the serial link so that PCIe protocol is not violated. But if the completions do not return
in order from remote PCIe link partner, then it may result in violation.
13.2.3.7 Transaction Address Alignment
The PCIESS imposes a limitation of a maximum of 128 byte outbound read/write command. However, if
the starting address is not aligned to an 8 byte boundary, then the maximum transaction size is reduced
to 120 bytes. Unspecified behavior will occur if misaligned transactions in outbound direction are not
limited to a maximum of 120 bytes.
13.2.3.8 Read Interleaving
Read interleaving refers to the process of returning split read responses from multiple transactions. This
implies that read data is not guaranteed to be sent in sequential order (data for one transaction to be
sent completely before the next). PCIE core is guaranteed to not interleave read responses if the
outbound read command/transaction size does not exceed the max transaction size configured in the
PCIE core. Currently this is configured as 128 bytes.
13.2.3.9 Endian Mode
The PCIESS is configured to operate in Little Endian mode. Most of the peripherals within the devices
are also configured in Little Endian mode. If user system is configured in "Big Endian" mode, then a
conversion is required to transform data format.
1282
Peripheral Component Interconnect Express (PCIe)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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