Table of Contents
Advertisement
www.ti.com
Table 16-27. Port Command Register (P#CMD) Field Descriptions (continued)
Bit
Field
Value
20
Reserved
0
19
MPSP
0
1
18
HPCP
0
1
17
PMA
0
1
16
CPD
0
15
CR
0-1
14
FR
0-1
13
MPSS
0
1
12-8
CCS
0-1Fh
7-5
Reserved
0
4
FRE
0-1
3
CLO
1
2
POD
0-1
1
SUD
0-1
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Description
Reserved. Since no CPD pins are bonded out for the device, this bit should be written with a zero value.
If need to implement CPD functionality, GPIO usage is recommended.
Mechanical Presence Switch Attached to Port.
Platform does not support a mechanical presence switch on this port.
Platform supports a mechanical presence switch attached to this port. When this bit is set to 1,
P0CMD.HPCP should also be set to 1.
Hot Plug.
Ports signal and power connectors are not externally accessible.
Ports signal and power connectors are externally accessible via a joint signal-power connector for
blindmate device hot plug.
Port Multiplier Attached.
Note: Software is responsible for detecting whether a Port Multiplier is present. There is no auto
detection.
When cleared to 0 by software, indicates that a Port Multiplier is not attached to this Port.
When set to 1 by software, indicates that a Port Multiplier is attached to this Port.
Since no CPD pins are bonded out for the device, this bit is always zero. if need to implement CPD
usage of GPIO is recommended.
Command List Running. When this bit is set to 1, the command list DMA engine for this Port is running.
See Synopsys spec for more detail.
FIS Receive Running. When set to 1, the FIS Receive DMA engine for this port is running. Refer to the
AHCI specification section 10.3.2 for details on when this bit is set and cleared by the Port.
Mechanical Presence Switch State. Reports the state of a mechanical presence switch attached to this
port as indicated by the P0_mp_switch input state (assuming CAP.SMPS = 1 and P0CMD.MPSP = 1).
If CAP.SMPS = 0, then this bit is cleared to 0. Software should only use this bit if both CAP.SMPS and
P0CMD.MPSP are set to 1.
Note: The reset of this bit may change based on the SATA_MP_SWITCH state at reset.
Switch is closed.
Switch is open.
Current Command Slot. This field is valid when P0CMD.ST is set to 1 and is set to the command slot
value of the command that is currently being issued by the Port. When P0CMD.ST transitions from 1 to
0, this field is reset to 0x00. After P0CMD.ST transitions from 0 to 1, the highest priority slot to issue
from next is command slot 0. After the first command has been issued, the highest priority slot to issue
from next is P0CMD.CCS+1. For example, after the Port has issued its first command, if CCS=0x00 and
P0CI is set to 0x3, the next command that will be issued is from command slot 1.
Reserved.
FIS Receive Enable. When set to 1, the Port may post received FISes into the FIS receive area pointed
to by P#FB. When cleared, received FISes are not accepted by the Port, except for the first D2H
register FIS after the initialization sequence, and no FISes are posted to the FIS receive area.
System software must not set this but until P#FB has been programmed with a valid pointer to the FIS
receive area, and if software wishes to move the base, this bit must first be cleared, and software must
wait for the P0CMD.FR bit to be cleared. Refer to the Synopsis spec for important restrictions on
changing P0CMD.FRE.
Command List Override. Setting this bit to 1 causes P0TFD.STS.BSY and P0TFD.STS.DRQ to be
cleared to 0. This allows a software reset to be transmitted to the device regardless of whether the BSY
and DRQ bits are still set in the P0TFD.STS register. This bit is cleared to 0 when P0TFD.STS.BSY and
P0TFD.STS.DRQ have been cleared to 0. A write to this register with a value of 0 has no effect.
This bit should only be set to 1 immediately prior to setting P0CMD.ST bit to 1 from a previous value of
0. Setting this bit to 1 at any other time is not supported and results in indeterminate behavior.
Power On Device. This bit is RW if cold presence detection is supported on this port as indicated by
P0CMD.CPD=1. This bit is RO 1 if cold presence detection is not supported and P0CMD.CPD=0. Note:
Since no CPD control/status related pins are bonded out on the device, this bit is read only. Usage of
GPIO is recommended if need to supplement CPD feature.
Spin-Up Device. This bit is read/write if staggered spin-up is supported as indicated by the CAP.SSS =
1. This bit is read-only 1 if staggered spin-up is not supported and CAP.SSS = 0. On an edge detect
from 0 to 1, the Port starts a COMRESET initialization sequence to the device. Clearing this bit causes
no action on the interface.
Note: the SUD bit is read-only 0 on power-up until CAP.SSS bit is written with the required value.
© 2011, Texas Instruments Incorporated
Registers
Serial ATA (SATA) Controller
1615
Advertisement
Table of Contents
