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Architecture
10.2.8.5.1 Loopback Mode Configurations
This is a summary of the settings required for digital loopback mode for TDM format:
•
The DLBEN bit in DLBCTL must be set to 1 to enable loopback mode.
•
The MODE bits in DLBCTL must be set to 01b for both the transmit and receive sections to use the
transmit clock and frame sync generator.
•
The ORD bit in DLBCTL must be programmed appropriately to select odd or even serializers to be
transmitters or receivers. The corresponding serializers must be configured accordingly.
•
The ASYNC bit in ACLKXCTL must be cleared to 0 to ensure synchronous transmit and receive
operations.
•
RMOD field in AFSRCTL and XMOD field in AFSXCTL must be set to 2h to 20h to indicate TDM
mode. Loopback mode does not apply to DIT or burst mode.
10.2.9 Reset Considerations
The McASP has two reset sources: software reset and hardware reset.
10.2.9.1 Software Reset Considerations
The transmitter and receiver portions of the McASP may be put in reset through the global control
register (GBLCTL). Note that a valid serial clock must be supplied to the desired portion of the McASP
(transmit and/or receive) in order to assert the software reset bits in GBLCTL. see
details on how to ensure reset has occurred.
The entire McASP module may also be reset through the Power and Sleep Controller (PSC). Note that
from the McASP perspective, this reset appears as a hardware reset to the entire module.
10.2.9.2 Hardware Reset Considerations
When the McASP is reset due to device reset, the entire serial port (including the transmitter and
receiver state machines, and other registers) is reset.
10.2.10 Setup and Initialization
This section discusses steps necessary to use the McASP module.
10.2.10.1 Considerations When Using a McASP
The following is a list of things to be considered for systems using a McASP:
10.2.10.1.1 Clocks
For each receive and transmit section:
•
External or internal generated bit clock and high frequency clock?
•
If internally generated, what is the bit clock speed and the high frequency clock speed?
•
Clock polarity?
•
External or internal generated frame sync?
•
If internally generated, what is frame sync speed?
•
Frame sync polarity?
•
Frame sync width?
•
Transmit and receive sync or asynchronous?
10.2.10.1.2 Data Pins
For each pin of each McASP:
•
McASP or GPIO?
•
Input or output?
1058
Multichannel Audio Serial Port (McASP)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
Section
10.2.10.2for
SPRUGX9 – 15 April 2011
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